Show HN:Interactive RISC-V CPU Visualizer (Sequential and Pipelined) https://ift.tt/nS5EFB7

Show HN:Interactive RISC-V CPU Visualizer (Sequential and Pipelined) I built an interactive RISC-V CPU visualizer for a course that lets you explore how instructions move through both a sequential and a 5-stage pipelined processor. You can step through execution, watch data hazards resolve, and see how branching and forwarding work in real time. The goal is to make CPU architecture learning more intuitive for students (and anyone who likes poking around pipelines). The whole verilog code and implementation details are available on the project report! Right now, the demo supports basic arithmetic, memory, and branch instructions, and includes two pre-programmed examples (a basic ALU demo and a Fibonacci pipeline program). Would love feedback on how to handle branching better, I remember crushing it due to deadline and it is not handled properly, but haven't looked at the code in-depth after that :p. I also want to do something similar for OS and write from scratch, been seeing a lot of post so any recommendations are appreciated :) Visualizers: https://mostlykiguess.github.io/RISC-V-Processor-Implementat... https://mostlykiguess.github.io/RISC-V-Processor-Implementat... Code: https://ift.tt/5Sxszql... https://mostlykiguess.github.io/RISC-V-Processor-Implementation/ October 27, 2025 at 11:04PM